With the development of the semiconductor industry, integrated circuits with higher performance and more powerful functions require greater element density. Thus, the sizes of the components need to be scaled further. The application of the core technology for the 32/22 nanometer process has been the inevitable trend for the development of integrated circuits, and is also one of the tasks that major international semiconductor companies and institutions compete to develop. Study on CMOS device gate engineering with the “high-k/metal gate” as the core technology is the most representative core process in 32/22 nanometer technology, and relevant research on materials, processes and structures has been widely conducted.
For an MOS device having a high-k/metal gate structure, the quality of high-k gate dielectric films, especially the oxygen vacancies and defect density of the high-k gate dielectric film, is essential to constantly improve the performance of the whole device. Currently, Hf-base high-k gate dielectric films have become the most potential candidate for industrialized materials, which have been successfully applied to the 45 nm process of Intel, and are expected to be applied to the next technology node. However, there exists serious problems caused by oxygen vacancies in the Hf-base high-k gate dielectric film, such as degradation of the threshold voltage and the mobility of channel carriers, and reduction of reliability, etc. Therefore, it has become a challenge to alleviate oxygen vacancies and defect density in the high-k gate dielectric film. Moreover, another significant parameter of an MOS device is Equivalent Oxide Thickness (EOT), and a sufficiently small EOT is essential to ensure scaling and performance enhancement of the MOS device. The enhancement for the quality of films and the reduction of the thickness for the SiOx interface layer of low dielectric constant are expected by continuous improvement of processes, in order to meet the requirements for the scaling of a 32/22 nanometer technology MOS device.
1. In the process for manufacturing an MOS device with a high-k metal structure in prior art, the high-k film layer are typically formed by a chemical method (atomic layer deposition or metal organic chemical vapor deposition), which may cause more defects and charge traps, and insufficient density and compactness of the high-k film. In order to improve the density and compactness of the high-k film and alleviate oxygen vacancies and defect traps, a postdeposition annealing (PDA) is typically required to be conducted in the temperature ranging from about 400 to 1100° C. However, in this process, oxygen in the annealing atmosphere will diffuse into the MOS device with a high-k metal gate structure under the high temperature, reach the SiO2/Si interface through the dielectric layer, and react with the silicon substrate to generate SiO2, thereby thickening the SiO2 interface layer. It disadvantageously leads to increase of EOT for the whole gate structure and degradation of the overall performance for the MOS device. On the other hand, a Post Metal Annealing_(PMA) may be conducted to the MOS device after deposition of a double metal gate, so as to improve the quality of the high-k gate dielectric film. However, this method only allows less oxygen to diffuse into the high-k gate dielectric film, which may partially supplement the oxygen vacancies and defect traps in the high-k gate dielectric film, and there is still a lot of oxygen vacancies and defect traps in the film.
Therefore, there is a need for a semiconductor device and a method of manufacturing the same to alleviate the oxygen vacancy defects in a high-k gate dielectric film.